The present invention relates to a field-effect transistor device, and more particularly to a field-effect transistor device having a plurality of MIS transistors forming a sense amplifier.
Most memory devices of a large capacity have a latch-type sense amplifier. FIG. 1 shows a latch-type sense amplifier having N-channel MOS transistors Q1 and Q2. Bit lines BL and BL are set at the same potential before data is transferred through them. Their potential varies when the data is transferred through them. Enable signal SAE is at the V.sub.DD level, e.g., 5 V. It falls to the V.sub.SS level, e.g., 0 V, in order to sense a potential difference corresponding to the data supplied to bit lines BL and BL. When signal SAE falls to the V.sub.SS level, MOS transistors Q1 and Q2 are activated thereby amplifying the potential difference to a predetermined level. More specifically, the sense amplifier sets one of the bit lines BL and BL at the V.sub.DD level, and sets the other bit line at the V.sub.SS level.
FIG. 2 is a plan view of the sense amplifier shown in FIG. 1, which is formed on a semiconductor memory chip. Wiring layers 10A and 10B are, for example, formed of aluminum, electrically insulated from semiconductor substrate 12, and extend in the same direction. Gate electrode 14A of MOS transistor Q2 and gate electrode 14B of MOS transistor Q1 are also insulated from substrate 12, and extend in the same direction as wiring layers 10A and 10B. Gate electrodes 14A and 14B are made, for example, of polycrystalline silicon. Both end portions of gate electrode 14A are overlapped by wiring layers 10A. Similarly, both end portions of gate electrode 14B are overlapped by wiring layers 10B. Aluminum wiring layers 10A are connected to the ends of gate electrode 14A by means of contact holes 16A, thereby forming bit line BL. Aluminum wiring layers 10B are coupled to the ends of gate electrode 14B by means of contact holes 16B, thereby forming bit line BL.
Drain region 18A and source region 18B of MOS transistor Q1 are formed within substrate 12, on the left and right sides of gate electrode 14B, respectively. Source region 20A and drain region 20B of MOS transistor Q2 are formed within substrate 12, on the left and right sides of gate electrode 14A, respectively. One of wiring layers 10A is connected to drain region 18A by means of contact hole 22A, and one of wiring layers 10B is connected to drain region 20B by means of contact hole 22B. Conductor layers 24A and 24B are formed in contact with source regions 18B and 20A. A wiring layer 26 is connected to conductor layer 24A by means of contact hole 28A and to conductor layer 24B by means of contact hole 28B. Wiring layers 10A, 10B and 26 and gate electrodes 14A and 14B are electrically insulated from one another by insulation layers (not shown).
Source region 18B and 20A and drain regions 18A and 20B have been simultaneously formed and self-aligned by ion-implantation of impurities, using gate electrodes 14A and 14B as masks. Ion implantation of this type is usually performed, as is illustrated in FIG. 3, in order to suppress the channeling effect. More specifically, the impurity ions are implanted into substrate 10 in the direction inclined to the surface of substrate 10 at a predetermined angle. Gate electrode 30 traps the impurity ions moving toward portion 31 of substrate 10. As a result, the implanted impurity ions are distributed in the substrate 10 asymmetrically with respect to the gate electrode 30.
As shown in FIG. 2, drain and source regions 18A and 18B of transistor Q1 are located on the right and left sides of gate electrode 14B, respectively, and, in contrast, drain and source regions 20B and 20A of transistor Q2 are positioned on the left and right sides of gate electrode 14A, respectively. Hence, transistors Q1 and Q2 inevitably have different characteristics. This difference is prominent, particularly when transistors Q1 and Q2 have a lightly-doped drain structure. For example, the driving ability (or, drain current) of transistor Q1 differs from that of transistor Q2 by about 30% at most.
Due to this great difference in driving ability, the sensitivity of the sense amplifier falls below the design value. If the sense amplifier is to function as desired, a greater potential difference must be provided between bit lines BL and BL. Also due to the difference in driving ability, the time required for providing a sufficient potential difference between bit lines BL and BL can become longer than the maximum tolerance value. This time depends on the sensed difference in potential, i.e., the data being transferred through bit lines BL and BL. It also depends on whether lines BL and BL are set at the V.sub.DD level and the V.sub.SS level, or vice versa. If this sense amplifier, which operates slowly, is used in a dynamic RAM whose memory cells must be refreshed frequently, it will cause the RAM to mulfunction.
FIG. 4 shows a sense amplifier of CMOS structure generally used. The MOS transistors forming this CMOS sense amplifier (or a MOS type flip-flop) usually have different driving abilities due to the ion implantation. Hence, the operation of the CMOS sense amplifier cannot always meet the design specifications.